1. Technical Field
Embodiments of the present invention are related to the field of electronic devices, and in particular, to integrated circuit packages.
2. Description of Related Art
Referring to FIG. 1, a land grid array (LGA) package 10 includes an integrated circuit (IC) chip or die 12 mounted on a substrate 14. The LGA package 10 has an array of planar, typically rectangular or circular, conductive “land pads” 15 in a base layer located on its underside to provide external surface contacts for direct mounting to a printed circuit board (PCB) or indirect mounting to the PCB through a socket. The substrate 14 includes die pads 16 in a top layer which are coupled to the die 12 via solder bumps 18 using flip chip mounting or other by other die-to-substrate interconnects, such as wire bonding or tape automated bonding (TAB). The land pads 15 and die pads 16 are dedicated to the various power, ground and input/output (I/O) signals of the IC die 12. The substrate 14 typically contains a Vss ground plane consisting of one or more ground layers, such as ground layers 20A, 20B, and 20C, and one or more I/O signal routing layers, such as signal routing layers 22A and 22B (partially shown), and one or more power layers, such as power layer 24. Vias 26 interconnect the various metal layers and pads to form electrical connections between the land and die pads 15 and 16.
In current designs for LGA packages, as illustrated by the LGA package 10, a large capacitance may exist between signal land pads 15 and a Vss ground layer 20A adjacent to the signal land pads 15. This large capacitance may degrade the high frequency signal performance. The planar dimension of the land pads 15 is large (1 mm diameter) and the thickness dimension of a dielectric layer 28 is thin (30 um); hence, the capacitance between the land pads 15 and the ground layer 20A may be large enough to impact signals in GHz frequency range.